View ISL62883IRTZ_8209261.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009-2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. multiphase pwm regulator for imvp-6.5? mobile cpus isl62883, isl62883b the isl62883 is a multiphase pwm buck regulator for miroprocessor core power supply. the multiphase buck converter uses interleaved phase to reduce the total output voltage ripple with each phase carrying a portion of the total load current, providing better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implementation area. the isl62883 uses two integrated gate drivers and an external gate driver to provide a complete solution. the pwm modulator is based on intersil's robust ripple regulator (r 3 ) technology?. compared with traditional modulators, the r 3 ? modulator commands variable switching frequency during load transients, achieving faster tran sient response. with the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. the isl62883 is fully compliant wi th imvp-6.5? specifications. it responds to psi# and dprslpvr signals by adding or dropping pwm3 and phase-2 respectively, ad justing overcurrent protection threshold accordingly, and enteri ng/exiting diode emulation mode. it reports the regulator output cu rrent through the imon pin. it senses the current by using either a discrete resistor or inductor dcr whose variation over temperature can be thermally compensated by a single ntc thermistor. it uses differential remote voltage sensing to accurately regulate the processor die voltage. the adaptive body di ode conduction time reduction function minimizes th e body diode conduction loss in diode emulation mode. user-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. in 2-phase configuration, the isl62883 offers the fb2 function to optimize 1-phase performance. the isl62883b has the same functions as the isl62883, but comes in a different package. features ? precision multiphase core voltage regulation - 0.5% system accuracy over-temperature - enhanced load line accuracy ? microprocessor voltage identification input - 7-bit vid input, 0.300v to 1.500v in 12.5mv steps - supports vid changes on-the-fly ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? supports psi# and dprslpvr modes ? superior noise immunity and transient response ? current monitor and thermal monitor ? differential remote voltage sensing ? high efficiency across entire load range ? programmable 1-, 2- or 3-phase operation ? two integrated gate drivers ? excellent dynamic current balance between phases ? fb2 function in 2-phase configuration to optimize 1-phase performance ? adaptive body diode conduction time reduction ? user-selectable overshoot reduction function ? small footprint 40 ld 5x5 or 48 ld 6x6 tqfn package ? pb-free (rohs compliant) applications ? notebook computers june 21, 2011 fn6891.4
isl62883, isl62883b 2 fn6891.4 june 21, 2011 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl62883hrtz 62883 hrtz -10 to +100 40 ld 5x5 tqfn l40.5x5 ISL62883IRTZ 62883 irtz -40 to +100 40 ld 5x5 tqfn l40.5x5 isl62883bhrtz 62883 bhrtz -10 to +100 48 ld 6x6 tqfn l48.6x6 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl62883 , isl62883b . for more information on msl please see techbrief tb363 . pin configurations isl62883 (40 ld tqfn) top view isl62883b (48 ld tqfn) top view 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 gnd pad (bottom) v r _ o n v i d 5 v i d 4 v i d 3 v i d 2 v i d 1 v i d 0 boot2 c l k _ e n # vr_tt# ntc ugate2 phase2 vssp2 vccp pwm3 lgate1 vssp1 comp isen2 sen3/fb2 fb vw psi# rbias pgood v i d 6 d p r s l p v r lgate2 phase1 isum- isum+ vin ugate1 boot1 imon vdd vsen rtn isen1 vr _on vid5 vi d4 v id3 v id2 vi d1 v id0 boot2 clk _e n# vr_tt# ntc ugate2 phase2 vssp2 vccp pwm3 lgate1 vssp1 comp isen3/fb2 fb vw psi# rbias pgood vid 6 d prs lpv r lgate2 phase1 isum- isum+ vin boot1 imon vdd vsen rtn isen1 1 48 2 3 4 5 6 7 8 9 10 36 35 34 33 32 31 30 29 28 27 47 46 45 44 43 42 41 40 39 13 14 15 16 17 18 19 20 21 22 23 24 11 12 38 37 26 25 isen2 gnd nc nc nc nc ugate1 nc nc nc (bottom)
isl62883, isl62883b 3 fn6891.4 june 21, 2011 pin function descriptions gnd signal common of the ic. unle ss otherwise stated, signals are referenced to the gnd pin. pgood power-good open-drain output in dicating when the regulator is able to supply regulated voltage. pull-up externally with a 680 resistor to vccp or 1.9k to 3.3v. psi# low load current indicator input. when asserted low, indicates a reduced load-current condition. for isl62883, when psi# is asserted low, pwm3 will be disabled. rbias 147k resistor to gnd sets internal current reference. vr_tt# thermal overload output indicator. ntc thermistor input to vr_tt# circuit. vw a resistor from this pin to comp programs the switching frequency (8k gives approximately 300khz). comp this pin is the output of the error amplifier. also, a resistor across this pin and gnd adjusts the overcurrent threshold. fb this pin is the inverting input of the error amplifier. isen3/fb2 when the isl62883 is configured in 3-phase mode, this pin is isen3. isen3 is the individual current sensing for phase 3. when the isl62883 is configured in 2- phase mode, this pin is fb2. there is a switch between the fb2 pin and the fb pin. the switch is on in 2-phase mode and is off in 1-phase mode. the components connecting to fb2 are used to adjust the compensation in 1-phase mode to achieve optimum performance. isen2 individual current sensing for phase-2. when isen2 is pulled to 5v vdd, the controller will disable phase-2 and allow other phases to operate. isen1 individual current sensing for phase-1. vsen remote core voltage sense input. connect to microprocessor die. rtn remote voltage sensing return. connect to ground at microprocessor die. isum- and isum+ droop current sense input. vdd 5v bias power. vin battery supply voltage, used for feed-forward. imon an analog output. imon outputs a current proportional to the regulator output current. boot1 connect an mlcc capacitor across the boot1 and the phase1 pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot1 pin, each time the phase1 pin drops below vccp minus the voltage dropped across the internal boot diode. ugate1 output of the phase-1 high-side mosfet gate driver. connect the ugate1 pin to the gate of the phase-1 high-side mosfet. phase1 current return path for the phase-1 high-side mosfet gate driver. connect the phase1 pin to the no de consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of phase-1. vssp1 current return path for the phase-1 low-side mosfet gate driver. connect the vssp1 pin to the source of the phase-1 low-side mosfet through a low impedance path, preferably in parallel with the trace connecting the lgate1 pin to the gate of the phase-1 low-side mosfet. lgate1 output of the phase-1 low-side mosfet gate driver. connect the lgate1 pin to the gate of the phase-1 low-side mosfet. pwm3 pwm output for channel 3. when pwm3 is pulled to 5v vdd, the controller will disable phase-3 an d allow other phases to operate. vccp input voltage bias for the internal gate drivers. connect +5v to the vccp pin. decouple with at le ast 1f of an mlcc capacitor to vssp1 and vssp2 pins respectively. lgate2 output of the phase-2 low-side mosfet gate driver. connect the lgate2 pin to the gate of the phase-2 low-side mosfet.
isl62883, isl62883b 4 fn6891.4 june 21, 2011 vssp2 current return path for the phase-2 converter low-side mosfet gate driver. connect the vssp2 pin to the source of the phase-2 low-side mosfet through a low impedance path, preferably in parallel with the trace connecting the lgate2 pin to the gate of the phase-2 low-side mosfet. phase2 current return path for the phase-2 high-side mosfet gate driver. connect the phase2 pin to the node consisting of the high-side mosfet source, the low-side mo sfet drain, and the output inductor of phase-2. ugate2 output of the phase-2 high-side mosfet gate driver. connect the ugate2 pin to the gate of the phase-2 high-side mosfet. boot2 connect an mlcc capacitor across the boot2 and the phase2 pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot2 pin, each time the phase2 pin drops below vccp minus the voltage dropped across the internal boot diode. vid0, vid1, vid2, vid3, vid4, vid5, vid6 vid input with vid0 = lsb and vid6 = msb. vr_on voltage regulator enable input. a high level logic signal on this pin enables the regulator. dprslpvr deeper sleep enable signal. a high level logic signal on this pin indicates that the microprocesso r is in deeper sleep mode. clk_en# open drain output to enable system pll clock. it goes low 13 switching cycles after v core is within 10% of v boot . nc no connect. bottom (on isl62883b) the bottom pad of isl62883b is electrically connected to the gnd pin inside the ic.
isl62883, isl62883b 5 fn6891.4 june 21, 2011 block diagram vid0 vid1 vid2 vid3 vid4 vid5 vid6 vr_on psi# dprslpvr mode control dac and soft start rtn e/a fb idroop current sense isum+ isum- imon imon comp driver shoot through protection driver pwm control logic driver shoot through protection driver pwm control logic protection pgood clk_en# adj. ocp threshold lgate1 phase1 ugate1 boot1 lgate2 phase2 ugate2 boot2 vsen clock vw isen1 isen3 isen2 current balance vin flt woc oc 2.5x vssp1 vssp2 woc oc vccp vin vdac modulator modulator modulator pwm3 ibal vin vdac ibal vin vdac ibal vin vdac comp vw comp comp comp pgood & clk_en# logic gnd vdd vr_tt# ntc 1.20v 1.24v 54a 6a rbias gain select 60ua number of phases ibal
isl62883, isl62883b 6 fn6891.4 june 21, 2011 absolute maximum rating s thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . . phase - 0.3v (dc) to boot . . . . . . . . . . . . . . . . . . . . . . . phase-5v (<20ns pulse width, 10j) to boot lgate voltage (lgate). . . . . . . . . . . . . . . . . . . . . . -0.3v (dc) to vdd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd +0.3v) open drain outputs, pgood, vr_tt#, clk_en# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v thermal resistance (typical) ja (c/w) jc (c/w) 40 ld tqfn package (notes 4, 5) . . . . . . . 32 3 48 ld tqfn package (notes 4, 5) . . . . . . . 29 2 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature isl62883hrtz, isl62883bhrtz . . . . . . . . . . . . . . . . .-10c to +100c ISL62883IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c junction temperature isl62883hrtz, isl62883bhrtz . . . . . . . . . . . . . . . . .-10c to +125c ISL62883IRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vdd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd vr_on = 1v 4 4.6 ma vr_on = 0v 1 a battery supply current i vin vr_on = 0v 1 a v in input resistance r vin vr_on = 1v 900 k power-on-reset threshold por r v dd rising 4.35 4.5 v por f v dd falling 4.00 4.15 v system and references system accuracy hrtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v -0.5 +0.5 % vid = 0.5v to 0.7375v -8 +8 mv vid = 0.3v to 0.4875v -15 +15 mv irtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v -0.8 +0.8 % vid = 0.5v to 0.7375v -10 +10 mv vid = 0.3v to 0.4875v -18 +18 mv v boot 1.0945 1.100 1.1055 v maximum output voltage v cc_core(max) vid = [0000000] 1.500 v minimum output voltage v cc_core(min) vid = [1100000] 0.300 v r bias voltage r bias = 147k 1.45 1.47 1.49 v
isl62883, isl62883b 7 fn6891.4 june 21, 2011 channel frequency nominal channel frequency f sw(nom) rfset = 7k , 3 channel operation, v comp = 1v 285 300 315 khz adjustment range 200 500 khz amplifiers current-sense amplifier input offset i fb = 0a -0.15 +0.15 mv error amp dc gain a v0 90 db error amp gain-bandwidth product gbw c l = 20pf 18 mhz isen imbalance voltage maximum of isens - minimum of isens 1 mv input bias current 20 na power good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pgood delay tpgd clk_en# low to pgood high 6.3 7.6 8.9 ms gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 lgate source current i lgsrc lgate - vssp = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h vsen rising above setpoint for >1ms 150 195 240 mv severe overvoltage threshold ov hs vsen rising for >2s 1.525 1.55 1.575 v oc threshold offset at rcomp = open circuit 3-phase configuration, isum- pin current 28.4 30.3 32.2 a 2-phase configuration, isum- pin current 18.3 20.2 22.1 a 1-phase configuration, isum- pin current 8.2 10.1 12.0 a current imbalance threshold one isen above another isen for >1.2ms 9 mv undervoltage threshold uv f vsen falling below setpoint for >1.2ms -355 -295 -235 mv logic thresholds vr_on input low v il(1.0v) 0.3 v electrical specifications operating conditions: vdd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62883, isl62883b 8 fn6891.4 june 21, 2011 vr_on input high hrtz v ih(1.0v) 0.7 v irtz v ih(1.0v) 0.75 v vid0-vid6, psi#, and dprslpvr input low v il(1.0v) 0.3 v vid0-vid6, psi#, and dprslpvr input high v ih(1.0v) 0.7 v pwm pwm3 output low v ol(5.0v) sinking 5ma 1.0 v pwm3 output high v oh(5.0v) sourcing 5ma 3.5 v pwm tri-state leakage pwm = 2.5v 2 a thermal monitor ntc source current ntc = 1.3v 53 60 67 a over-temperature threshold v (ntc) falling 1.18 1.2 1.22 v vr_tt# low output resistance r tt i = 20ma 6.5 9 clk_en# output levels clk_en# low output voltage v ol i = 4ma 0.26 0.4 v clk_en# leakage current i oh clk_en# = 3.3v -1 1 a current monitor imon output current i imon isum- pin current = 20 a 108 120 132 a isum- pin current = 10 a 51 60 69 a isum- pin current = 5 a 22 30 37.5 a imon clamp voltage v imonclamp 1.1 1.15 v current sinking capability 275 a inputs vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v 0 1 a vidx leakage current i vidx vidx = 0v -1 0a vidx = 1v 0.45 1 a psi# leakage current i psi# psi# = 0v -1 0a psi# = 1v 0.45 1 a dprslpvr leakage current i dprslpvr dprslpvr = 0v -1 0a dprslpvr = 1v 0.45 1 a slew rate slew rate (for vid change) sr 56.5 mv/s note: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications operating conditions: vdd = 5v, t a = -40c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62883, isl62883b 9 fn6891.4 june 21, 2011 gate driver timing diagram pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr
isl62883, isl62883b 10 fn6891.4 june 21, 2011 simplified application circuits l2 l1 v o isen3 phase2 ugate2 rsum2 rsum1 rn cn ri l3 rs3 cs3 rsum3 boot2 (bottom pad) vss v+5 vcc ugate lgate phase boot pwm fccm gnd vin isl6208 lgate2 isen2 phase1 ugate1 boot1 lgate1 isen1 pwm3 isum+ isum- fb vsen comp rdroop rfset vw rtn pgood vr_on dprslpvr psi# vids rbias ntc clk_en# v+5 vin vin vdd imon clk_en# vid<0:6> psi# dprslpvr vr_on pgood rimon vsssense vccsense imon vr_tt# vr_tt# v+5 vccp vssp2 vssp1 o c isl62883 rbias rntc o c ris cis rs2 cs2 rs1 cs1 figure 1. typical application circuit using dcr sensing figure 2. typical application circuit using resistor sensing isen3 phase2 ugate2 rsum2 rsum1 cn ri rsum3 boot2 (bottom pad) vss v+5 vcc ugate lgate phase boot pwm fccm gnd vin isl6208 lgate2 isen2 phase1 ugate1 boot1 lgate1 isen1 pwm3 isum+ isum- fb vsen comp rdroop rfset vw rtn pgood vr_on dprslpvr psi# vids rbias ntc clk_en# v+5 vin vin vdd imon clk_en# vid<0:6> psi# dprslpvr vr_on pgood rimon vsssense vccsense imon vr_tt# vr_tt# v+5 vccp vssp2 vssp1 isl62883 rbias rntc o c ris cis l2 l1 v o l3 rsen3 rsen2 rsen1 rs3 cs3 rs2 cs2 rs1 cs2
isl62883, isl62883b 11 fn6891.4 june 21, 2011 theory of operation multiphase r 3 ? modulator the isl62883 is a multiphase regu lator, which implements intel? imvp-6.5? protocol. it can be programmed for 1-, 2- or 3-phase operation for microprocessor core applications. it uses intersil patented r 3 ? (robust ripple regulator?) modulator. the r 3 ? modulator combines the best fe atures of fixed frequency pwm and hysteretic pwm while eliminat ing many of their shortcomings. figure 3 conceptually shows the isl62883 multiphase r 3 ? modulator circuit, and figure 4 shows the operation principles. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between the two pins. this voltage window is called vw window in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one- shot master clock signal. a phase sequencer distributes the master clock signal to the slave circuits. if the isl62883 is in 3-phase mode, the master clock signal will be distributed to the three phases, and the clock1~3 signals will be 120 out-of- phase. if the isl62883 is in 2-phase mode, the master clock signal will be distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out- of-phase. if the isl62883 is in 1-phase mode, the master clock signal will be distributed to phases 1 only and be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs figure 3. r 3 ? modulatorcircuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3 figure 4. r 3 ? modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw figure 5. r 3 ? modulatoroperation principles in load insertion response comp vcrm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw
isl62883, isl62883b 12 fn6891.4 june 21, 2011 voltage v crs hits vw, the slave circui t turns off the pwm pulse, and the current source discharges c rs . since the isl62883 works with v crs , which are large-amplitude and noise-free synthe sized signals, the isl62883 achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the isl62883 has an er ror amplifier that allows the controller to maintain a 0.5% output voltage accuracy. figure 5 shows the operation principles during load insertion response. the comp voltage ri ses during load insertion, generating the master clock sign al more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency pw m controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, the comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the vw voltage falls, reducing the current pwm pulse width. this kind of behavior gives the isl62883 excellent response speed. the fact that all the phases share the same vw window voltage also ensures excellent dynamic current balance among phases. diode emulation and period stretching isl62883 can operate in diode emulation (de) mode to improve light load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and doesn?t not allow reverse current, emulating a di ode. as figure 6 shows, when lgate is on, the low-side mosfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the isl62883 monitors the current through monitoring the phase node voltag e. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enough, as figure 6 shows, the inductor current will reach and stay at ze ro before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 7 shows the operation principle in diode emulation mode at light load. the load gets incremen tally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triangle the same in the three cases. the isl62883 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light load efficiency. start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins when vr_on exceeds the 3.3v logic high threshold. the isl62883 uses digital soft start to ramp up dac to the boot voltage of 1.1v at about 2.5m v/s. once the output voltage is within 10% of the boot voltage for 13 pwm cycles (43s for frequency = 300khz), clk_en# is pulled low and dac slews at 5mv/s to the voltage set by the vid pins. pgood is asserted high in approximatel y 7ms. figure 8 shows the typical start-up timing. similar results occur if vr_on is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. figure 6. diode emulation ugate phase il lgate figure 7. period stretching il il vcrs il vcrs vcrs vw ccm/dcm boundary light dcm deep dcm vw vw figure 8. soft-start waveforms vdd vr_on dac 800s 2.5mv/s vboot 5mv/s vid command voltage 90% 13 switching cycles clk_en# pgood ~7ms
isl62883, isl62883b 13 fn6891.4 june 21, 2011 voltage regulation and load line implementation after the start sequence, the isl62883 regulates the output voltage to the value set by th e vid inputs per table 1. the isl62883 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.5v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. table 1. vid table vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) 00000001. 5000 00000011.4875 00000101.4750 00000111. 4625 00001001. 4500 00001011.4375 00001101. 4250 00001111.4125 00010001. 4000 00010011.3875 00010101.3750 00010111. 3625 00011001. 3500 00011011.3375 00011101. 3250 00011111.3125 00100001. 3000 00100011.2875 00100101.2750 00100111. 2625 00101001. 2500 00101011.2375 00101101. 2250 00101111.2125 00110001. 2000 00110011.1875 00110101.1750 00110111.1625 00111001. 1500 00111011.1375 00111101.1250 00111111.1125 01000001.1000 01000011.0875 01000101.0750 01000111. 0625 01001001.0500 01001011.0375 01001101.0250 01001111.0125 01010001.0000 01010010.9875 01010100.9750 01010110. 9625 01011000. 9500 01011010.9375 01011100. 9250 01011110.9125 01100000. 9000 01100010.8875 01100100.8750 01100110. 8625 01101000. 8500 01101010.8375 01101100. 8250 01101110.8125 01110000. 8000 01110010.7875 01110100.7750 01110110.7625 01111000. 7500 01111010.7375 01111100. 7250 01111110.7125 10000000. 7000 10000010.6875 10000100. 6750 10000110. 6625 10001000. 6500 10001010.6375 10001100. 6250 10001110.6125 10010000. 6000 10010010.5875 10010100.5750 10010110. 5625 10011000. 5500 10011010.5375 10011100. 5250 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v)
isl62883, isl62883b 14 fn6891.4 june 21, 2011 as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to the load current to achieve the load line. the isl62883 can sense the inductor current through the intrinsic dc resistance (dcr) resistance of the inductors figure 1 shows on page 10 or through resistors in series with the inductors as figure 2 shows also on page 10. in both methods, capacitor c n voltage represents the inductor total currents. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for lo ad line implementation, current monitor and overcurrent protection. figure 9 shows the load line implementation. the isl62883 drives a current source i droop out of the fb pin, described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop of: v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can both change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. 10011110.5125 10100000. 5000 10100010.4875 10100100.4750 10100110. 4625 10101000. 4500 10101010.4375 10101100. 4250 10101110.4125 10110000. 4000 10110010.3875 10110100.3750 10110110. 3625 10111000. 3500 10111010.3375 10111100. 3250 10111110.3125 11000000. 3000 11000010.2875 11000100.2750 11000110. 2625 11001000. 2500 11001010.2375 11001100. 2250 11001110.2125 11010000. 2000 11010010.1875 11010100.1750 11010110.1625 11011000. 1500 11011010.1375 11011100.1250 11011110.1125 11100000.1000 11100010.0875 11100100.0750 11100110. 0625 11101000. 0500 11101010.0375 11101100. 0250 11101110.0125 11110000. 0000 11110010. 0000 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) 11110100. 0000 11110110. 0000 11111000. 0000 11111010. 0000 11111100. 0000 11111110. 0000 table 1. vid table (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v o (v) figure 9. differential sensing and load line implementation x 1 e/a i droop 2xv cn r i ---------------- = (eq. 1) v droop r droop i droop = (eq. 2)
isl62883, isl62883b 15 fn6891.4 june 21, 2011 differential sensing figure 9 also shows the differ ential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity gain differential amplifier senses the vss sense voltage and add it to the dac output. the error amplifier regulates the inverting and the non-inverting input voltages to be equal as shown in equation 3: rewriting equation 3 and substitution of equation 2 gives: equation 4 is the exact equa tion required for load line implementation. the vcc sense and vss sense signals come fr om the processor die. the feedback will be open circuit in the absence of the processor. as shown in figure 9, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and add another ?cat ch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without a processor installed. phase current balancing the isl62883 monitors individu al phase average current by monitoring the isen1, isen2, and isen3 voltages. figure 10 shows the current balancing circuit recommended for isl62883. each phase node voltage is averaged by a low-pass filter consisting of r s and c s , and presented to the corresponding isen pin. r s should be routed to inductor phase-node pad in order to eliminate the effect of phase node parasitic pcb dcr. equations 5 thru 7 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are inductor dcr; r pcb1 , r pcb2 and r pcb3 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. the isl62883 will adjust the phase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus to achieve i l1 =i l2 =i l3 , when there are r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . using same components for l1, l2 and l3 will provide a good match of r dcr1 , r dcr2 and r dcr3 . board layout will determine r pcb1 , r pcb2 and r pcb3 . it is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 =r pcb3 . sometimes, it is difficult to implement symmetrical layout. for the circuit shown in figure 10, asymmetric layout causes different r pcb1 , r pcb2 and r pcb3 thus current imbalance. figure 11 shows a differential-sensing current balancing circuit recommended for isl62883. the cu rrent sensing tr aces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of three sources: its own phase inductor phase-node pad, and the other two phases inductor output side pads. equations 8 thru 10 give the isen pin voltages: the isl62883 will make v isen1 = v isen2 = v isen3 as in: rewriting equation 11 gives: and rewriting equation 12 gives: combining equations 13 and 14 gives : therefore: vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop ? = (eq. 4) figure 10. current balancing circuit internal to ic v o isen3 l3 rs cs isen2 rs cs isen1 rs cs l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 v isen1 r dcr1 r pcb1 + () i l1 = (eq. 5) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 6) v isen3 r dcr3 r pcb3 + () i l3 = (eq. 7) figure 11. differential-sensing current balancing circuit internal to ic v o isen3 l3 rs cs isen2 rs cs isen1 rs cs l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 rs rs rs rs rs rs v3p v3n v2p v2n v1p v1n v isen1 v 1p v 2n v 3n ++ = (eq. 8) v isen2 v 1n v 2p v 3n ++ = (eq. 9) v isen3 v 1n v 2n v 3p ++ = (eq. 10) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 11) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 12) v 1p v 1n ? v 2p v 2n ? = (eq. 13) v 2p v 2n ? v 3p v 3n ? = (eq. 14) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 15) r dcr1 i l1 r dcr2 i l2 r dcr3 i l3 == (eq. 16)
isl62883, isl62883b 16 fn6891.4 june 21, 2011 current balancing (i l1 =i l2 =i l3 ) will be achieved when there is r dcr1 =r dcr2 =r dcr3 . r pcb1 , r pcb2 and r pcb3 will not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, r 3 ? modulator can naturally achieve excellent current balancing during steady state and dynamic operations. figure 12 shows current balancing performance of the isl62883 evaluation board with load transi ent of 12a/51a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at low rep rate, but cannot keep up when the rep rate gets into the hundred-khz range, where it?s out of the control loop bandwidth. the controller achieves excellent current balancing in all cases. ccm switching frequency the r fset resistor between the comp and the vw pins sets the sets the vw windows size, therefor e sets the switching frequency. when the isl62883 is in contin uous conduction mode (ccm), the switching frequency is not ab solutely constant due to the nature of the r 3 ? modulator. as explained in the multiphase r 3 ? modulator section, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. on the other hand, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load , etc. changes. the variation is usually less than 15% and doesn?t have any significant effect on output voltage ripple magnitude. equation 17 gives an estimate of the frequency-setting resistor r fset value. 8k r fset gives approximately 300khz switching frequency. lower resistance gives higher switching frequency. phase count configurations the isl62883 can be configured fo r 3-, 2- or 1-phase operation. for 2-phase configuration, tie th e pwm3 pin to 5v. phase-1 and phase-2 pwm pulses are 180 out-of-phase. in this configuration, the isen3/fb2 pin (p in 9) serves the fb2 function. for 1-phase configuration, tie the pwm3 and isen2 pins to 5v. in this configuration, only phase-1 is active. the isen3/fb2, isen2, and isen1 pins are not used because there is no need for either current balancing or fb2 function. figure 12. isl62883 evaluation board current balancing during dynamic operation. ch1: il1, ch2: i load , ch3: il2, ch4: il3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz r fset k () period s () 0.29 ? () 2.65 = (eq. 17)
isl62883, isl62883b 17 fn6891.4 june 21, 2011 modes of operation table 2 shows the isl62883 operational modes, programmed by the logic status of the psi# an d the dprslpvr pins. in 3-phase configuration, the isl62883 enters 2-phase ccm for (psi# = 0 and dprslpvr = 0) by dropping pwm3 and operating phases 1 and 2 180 out-of-phase. it also reduces the overcurrent and the way-overcurrent protection levels to 2/3 of the initial values. the isl62883 enters 1-phase de mode when dprslpvr = 1. it drops phases 2 and 3, and reduces the overcurrent and the way- overcurrent protection levels to 1/3 of the initial values. in 2-phase configuration, the isl62883 enters 1-phase ccm for (psi# = 0 and dprslpvr = 0). it drops phase-2 and reduces the overcurrent and the way-overcurrent protection levels to 1/2 of the initial values. the isl62883 enters 1-phase de mode when dprslpvr = 1 by dropping phase 2. in 1-phase configuration, the isl62883 does not change the operational mode when the psi# si gnal changes status. it enters 1-phase de mode when dprslpvr = 1. dynamic operation the isl62883 responds to vid changes by slewing to the new voltage at 5mv/s slew rate. as the output approaches the vid command voltage, the dv/dt moderates to prevent overshoot. geyserville-iii transiti ons commands one lsb vid step (12.5mv) every 2.5s, controlling the effective dv/dt at 5mv/s. the isl62883 is capable of 5mv/s slew rate. when the isl62883 is in de mode, it will actively drive the output voltage up when the vid changes to a higher value. it?ll resume de mode operation after reaching the new voltage level. if the load is light enough to warrant dcm, it will enter dcm after the inductor current has crossed zero for four consecutive cycles. the isl62883 will remain in de mo de when the vid changes to a lower value. the output voltage will decay to the new value and the load will determine the slew rate. during load insertion response, th e fast clock function increases the pwm pulse response speed. the isl62883 monitors the vsen pin voltage and compares it to 100ns - filtered version. when the unfiltered version is 20mv below the filtered version, the controller knows there is a fast voltage dip due to load insertion, hence issues an addi tional master clock signal to deliver a pwm pulse immediately. the r 3 ? modulator intrinsically has voltage feed forward. the output voltage is insensitive to a fast slew rate input voltage change. protections the isl62883 provides overcurrent, current-balance, undervoltage, overvoltage, and over-temperature protections. the isl62883 determines overcurrent protection (ocp) by comparing the average value of the droop current i droop with an internal current source threshold. it declares ocp when i droop is above the threshold for 120s. a resistor r comp from the comp pin to gnd programs the ocp current source threshold, as table 3 shows. it is recommended to use the nominal r comp value. the isl62883 detects the r comp value at the beginning of start up, and sets the internal ocp threshol d accordingly. it remembers the r comp value until the vr_on signal drops below the por threshold. the default ocp threshold is the value when r comp is not populated. it is recommended to scale the droop current i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. for overcurrent conditions above 2.5 times the ocp level, the pwm outputs will immediately shut off and pgood will go low to maximize protection. this protec tion is also referred to as way-overcurrent protection or fa st-overcurrent protection, for short-circuit protections. the isl62883 monitors the isen pin voltages to determine current-balance protection. if the isen pin voltage difference is greater than 9mv for 1ms, the controller will declare a fault and latch off. the isl62883 will declare undervoltage (uv) fault and latch off if the output voltage is less than the vid set value by 300mv or more for 1ms. it?ll turn off the pwm outputs and dessert pgood. the isl62883 has two levels of overvoltage protections. the first level of overvoltage protection is referred to as pgood overvoltage protection. if the output voltage exceeds the vid set table 2. isl62883 modes of operation configuration psi# dprslpvr operational mode 3-phase configuration 0 0 2-phase ccm 011-phase de 1 0 3-phase ccm 111-phase de 2-phase configuration 0 0 1-phase ccm 011-phase de 1 0 2-phase ccm 111-phase de 1-phase configuration 0 0 1-phase ccm 011-phase de 1 0 1-phase ccm 111-phase de table 3. isl62883 ocp threshold r comp ocp threshold (a) min. (k ) nominal (k ) max. (k ) 1-phase mode 2-phase mode 3-phase mode none none 20 40 60 320 400 480 22.7 45.3 68 210 235 260 20.7 41.3 62 155 165 175 18 36 54 104 120 136 20 37.33 56 78 85 92 22.7 38.7 58 62 66 70 20.7 42.7 64 45 50 55 18 44 66
isl62883, isl62883b 18 fn6891.4 june 21, 2011 value by +200mv for 1ms, the isl62883 will declare a fault and dessert pgood. the isl62883 takes the same acti ons for all of the above fault protections: desertion of pgood and turn-off of the high-side and low-side power mosfets. any resi dual inductor current will decay through the mosfet body diodes. these fault conditions can be reset by bringing vr_on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. the second level of overvoltage protection is different. if the output voltage exceeds 1.55v, the isl62883 will immediately declare an ov fault, dessert pg ood, and turn on the low-side power mosfets. the low-side power mosfets remain on until the output voltage is pulled down below 0.85v when all power mosfets are turned off. if the output voltage rises above 1.55v again, the protection process is repeated. this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. resetting vr_on cannot clear the 1.55v ovp. only resetting v dd will clear it. the 1.55v ovp is active all the time when the controller is enabled, even if on e of the other faults have been declared. this ensures that the processor is protected against high-side power mosfet leakage while the mosfets are commanded off. the isl62883 has a thermal throttlin g feature. if the voltage on the ntc pin goes below the 1.18v ot threshold, the vr_tt# pin is pulled low indicating the need for thermal throttling to the system. no other action is taken within the isl62883 in response to ntc pin voltage. table 4 summarizes the fault protections. . current monitor the isl62883 provides the current monitor function. the imon pin outputs a high-speed analog cu rrent source that is 3 times of the droop current flowing out of the fb pin. thus equation 18: as figures 1 and 2 show, a resistor r imon is connected to the imon pin to convert the imon pin current to voltage. a capacitor can be paralleled with r imon to filter the voltage information. the imvp-6.5? specification requires that the imon voltage information be referenced to vsssense. the imon pin voltage range is 0v to 1.1v. a clamp circuit prevents the imon pin voltage from going above 1.1v. fb2 function the fb2 function is only avai lable when the isl62883 is in 2-phase configuration, when pin 9 serves the fb2 function instead of the isen3 function. figure 13 shows the fb2 function . a switch (called fb2 switch) turns on to short the fb and the fb2 pins when the controller is in 2-phase mode. capacitors c3.1 and c3.2 are in parallel, serving as part of the compensator. when the controller enters 1-phase mode, the fb2 switch turns off, removing c3.2 and leaving only c3.1 in the compensator. the compensator gain will increase with the removal of c3.2. by properly sizing c3.1 and c3.2, the compensator cab be optimal for both 2-phase mode and 1-phase mode. when the fb2 switch is off, c3.2 is disconnected from the fb pin. however, the controller still actively drives the fb2 pin voltage to follow the fb pin voltage such that c3.2 voltage always follows c3.1 voltage. when the controlle r turns on the fb2 switch, c3.2 will be reconnected to the compensator smoothly. the fb2 function ensures excellent transient response in both 2-phase mode and 1-phase mode. if one decides not to use the fb2 function, simply populate c3.1 only. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative and the amount is the mosfet r dson voltage drop, which is proportional to the inductor current. a phase comparator insi de the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the low-side mosfet turns off, it?ll flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it?ll flow th rough the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. the controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase table 4. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vdd toggle way-overcurrent (2.5xoc) <2s overvoltage +200mv 1ms undervoltage -300mv phase current unbalance overvoltage 1.55v immediately low-side mosfet on until v core <0.85v, then pwm tri-state, pgood latched low. vdd toggle over-temperature 1ms n/a i imon 3i droop = (eq. 18) figure 13. fb2 function in 2-phase mode r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen controller in 2-phase mode controller in 1-phase mode
isl62883, isl62883b 19 fn6891.4 june 21, 2011 comparator threshold voltage acco rdingly in iterative steps such that the low-side mosfet body diode conducts fo r approximately 40ns to minimize the body diode-related loss. overshoot reduction function the isl62883 has an optional overshoot reduction function. using r bias = 47k enables this function and using r bias =147k disables this function. when a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. the inductor current freewheels through the low-side mosfet during this period of time. the overshoot reduction function turns off the low-side mosfet during the output voltage overshoot, forcing the inductor current to freewheel through the low-side mosfet body diode. si nce the body diode voltage drop is much higher than mosfet r dson voltage drop, more energy is dissipated on the low-side mosfet therefore the output voltage overshoot is lower. if the overshoot reduction function is enabled, the isl62883 monitors the comp pin voltage to determine the output voltage overshoot condition. the comp voltage will fall and hit the clamp voltage when the output voltag e overshoots. the isl62883 will turn off lgate1 and lgate2, and tri-state pwm3 when comp is being clamped. all the low-side mosfets in the power stage will be turned off. when the output voltage has reached its peak and starts to come down, the comp voltage starts to rise and is no longer clamped. the isl6288 3 will resume normal pwm operation. when psi# is low, indicating a low power state of the cpu, the controller will disable the overshoot reduction function as large magnitude transient event is not expected and overshoot is not a concern. while the overshoot reduction function reduces the output voltage overshoot, energy is dissipated on the low-side mosfet, causing additional power loss. the more frequent transient event, the more power loss dissipated on the low-side mosfet. the mosfet may face severe thermal stress when tr ansient events happen at a high repetitive rate. user discretion is advised when this function is enabled. key component selection r bias the isl62883 uses a resistor (1% or better tolerance is recommended) from the rbias pin to gnd to establish highly accurate reference current sources inside the ic. using r bias =47k enables the overshoot redu ction function and using r bias = 147k disables this function. do not connect any other components to this pin. do not connect any capacitor to the rbias pin as it will create instability. care should be taken in layout that the resistor is placed very close to the rbias pin and that a good quality signal ground is connected to the opposite side of the r bias resistor. r is and c is as figures 1 and 2, show, the isl62883 needs the r is -c is network across the isum+ and th e isum- pins to stabilize the droop amplifier. the preferred values are r is = 82.5 and c is = 0.01f. slight deviations from the recommended values are acceptable. large deviations may result in instability. inductor dcr current-sensing network figure 14 shows the inductor dcr current-sensing network for a 3-phase solution. an inductor cu rrent flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to a ccurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summ ing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature-compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ~10 r o to create quality signals. since r o value is much smaller than the rest of the curr ent sensing circuit, the following analysis will ignore it for simplicity. the summed inductor current information is presented to the capacitor c n . equations 19 thru 23 describe the frequency-domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. figure 14. dcr current-sensing network cn rsum ro rntcs rntc rp dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn v cn s () r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 19) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - = (eq. 20) a cs s () 1 s l ------ + 1 s sns ------------ + ---------------------- = (eq. 21)
isl62883, isl62883b 20 fn6891.4 june 21, 2011 transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc values decreases as its temp erature decreases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represent the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature- compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage, so the droop circuit has higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k , r p = 11k , r ntcs = 2.61k and r ntc = 10k (ert-j1vr103j). the ntc network parameters may need to be fine tuned on ac tual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltag e drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current-sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient resp onse. transfer function a cs (s) has a pole sns and a zero l . one needs to match l and sns so a cs (s) is unity gain at all frequencies. by forcing l equal to sns and solving for the solution, equation 24 solves for the value of cn . for example, given n = 3, r sum = 3.65k , r p =11k , r ntcs =2.61k , r ntc = 10k , dcr = 0.88m and l = 0.36h, equation 24 gives c n = 0.406f. assuming the compensator design is correct, figure 15 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) will not accurately represent real-time i o (s) and will worsen the transient response. figure 16 shows the load transient response when c n is too small. v core will sag excessively upon load insertion and may create a system failure. figure 17 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. l dcr l ----------- - = (eq. 22) sns 1 r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- c n ------------------------------------------------------ = (eq. 23) c n l r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- dcr ----------------------------------------------------------- - = (eq. 24) figure 15. desired load transient response waveforms o i v o figure 16. load transient response when c n is too small o i v o figure 17. load transient response when c n is too large o i v o figure 18. output voltage ring back problem o i v o l i ring back
isl62883, isl62883b 21 fn6891.4 june 21, 2011 figure 18 shows the output voltage ring back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first order system fashion due to the nature of current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore it pulls v o back to the level dictated by i l , causing the ring back problem. this phenom enon is not observed when the output capacitor have very low esr and esl, such as all ceramic capacitors. figure 19 shows two optional circuits for reduction of the ring back. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 19 shows that two capacitors c n.1 and c n.2 are in parallel. resistor r n is an optional component to reduce the v o ring back. at steady state, c n.1 +c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as explained in figure 16, v o tends to dip when c n is too small, and this effect will reduce the v o ring back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning th e load transient response waveforms on an actual board. resistor current-sensing network figure 20 shows the resistor current-sensing network for a 3-phase solution. each inductor has a series current-sensing resistor r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a a filter for noise attenuation. equations 25 thru 27 give v cn (s) expression: transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value will not have significant variation over temperature, so there is no need for the ntc network. the recommended values are r sum =1k and c n = 5600pf. overcurrent protection refer to equation 1 and figures 9, 14 and 20; resistor r i sets the droop current i droop . table 3 shows the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 60a for 3-phase solution. we will design i droop to be 38.8a at full load, so the ocp trip level is 1.55 times of the full load current. for inductor dcr sensing, equation 28 gives the dc relationship of v cn (s) and i o (s). figure 19. optional circuits for ring back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional figure 20. resistor cu rrent-sensing network cn rsum ro dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn rsen rsen rsen v cn s () r sen n ------------ i o s () a rsen s () = (eq. 25) a rsen s () 1 1 s sns ------------ + ---------------------- = (eq. 26) rsen 1 r sum n -------------- c n --------------------------- = (eq. 27) v cn r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o = (eq. 28)
isl62883, isl62883b 22 fn6891.4 june 21, 2011 substitution of equation 28 in to equation 1 gives equation 29: therefore : substitution of equation 20 and application of the ocp condition in equation 30 gives equation 31: where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 3, r sum = 3.65k , r p = 11k , r ntcs =2.61k , r ntc =10k , dcr = 0.88m , i omax =51a and i droopmax = 40.9a, equation 31 gives r i = 606 . for resistor sensing, equation 32 gives the dc relationship of v cn (s) and i o (s). substitution of equation 32 into equation 1 gives equation 33: therefore: substitution of equation 34 and application of the ocp condition in equation 30 gives : where i omax is the full load current, i droopmax is the corresponding droop current. for example, given n = 3, r sen =1m , i omax =51a and i droopmax = 40.9a, equation 35 gives r i =831 . a resistor from comp to gnd can adjust the internal ocp threshold, providing another dimension of fine-tune flexibility. table 3 shows the detail. it is recommended to scale i droop such that the default ocp threshold gives approximately the desired ocp level, then use r comp to fine tune the ocp level if necessary. load line slope refer to figure 9. for inductor dcr sensing, substitution of equation 29 into equation 2 gives the load line slope expression : for resistor sensing, substitution of equation 33 into equation 2 gives the load line slope expression : substitution of equation 30 and rewriting equation 36, or substitution of equation 34 and rewriting equation 37 gives the same result in equation 38: one can use the full load condition to calculate r droop . for example, given i omax =51a, i droopmax = 40.9a and ll = 1.9m , equation 38 gives r droop =2.37k . it is recommended to start with the r droop value calculated by equation 38, and fine tune it on the actual board to get accurate load line slope. one should record the output voltage readings at no load and at full load for load line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. current monitor refer to equation 18 for the imon pin current expression. refer to figures 1 and 2, the imon pin current flows through r imon . the voltage across r imon is expressed in equation 39: rewriting equation 38 gives equation 40: substitution of equation 40 into equation 39 gives equation 41: rewriting equation 41 and application of full load condition gives equation 42: for example, given ll = 1.9m , r droop =2.37k , v rimon = 963mv at i omax = 51a, equation 42 gives r imon =7.85k . a capacitor c imon can be paralleled with r imon to filter the imon pin voltage. the r imon c imon time constant is the user?s choice. it is recommended to have a time co nstant long enough such that switching frequency ripples are removed. compensator figure 15 shows the desired load transient response waveforms. figure 21 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load line slope ll, i.e. constant output impedance, in the entire frequency range, v o will have square response when i o has a square change. i droop 2 r i ---- - r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - i o = (eq. 29) r i 2r ntcnet dcr i o nr ntcnet r sum n -------------- + ?? ?? i droop ------------------------------------------------------------------------------- - = (eq. 30) r i 2 r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum n -------------- + ?? ?? ?? i droopmax ------------------------------------------------------------------------------------------------------------------------- = (eq. 31) v cn r sen n ------------ i o = (eq. 32) i droop 2 r i ---- - r sen n ------------ i o = (eq. 33) r i 2r sen i o ni droop --------------------------- = (eq. 34) r i 2r sen i omax ni droopmax -------------------------------------- = (eq. 35) ll v droop i o ----------------- - 2r droop r i ---------------------- r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - == (eq. 36) ll v droop i o ----------------- - 2r sen r droop nr i ----------------------------------------- == (eq. 37) r droop i o i droop --------------- - ll = (eq. 38) v rimon 3i droop r imon = (eq. 39) i droop i o r droop ------------------ ll = (eq. 40) v rimon 3i o ll r droop -------------------- - r imon = (eq. 41) r imon v rimon r droop 3i o ll -------------------------------------------- = (eq. 42)
isl62883, isl62883b 23 fn6891.4 june 21, 2011 intersil provides a microsoft excel- based spreadsheet to help design the compensator and the current sensing network, so the vr achieves constant output impeda nce as a stable system. please contact intersil application support at www.intersil.com/design/ . figure 24 shows a screenshot of the spreadsheet. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 22 conceptually shows t1(s) measurement set-up and figure 23 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. t(1) is measured after the summing node, and t2(s) is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can be actually measured on an isl62883 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s) and has more meaning of system stability. t2(s) is the voltage loop gain with closed droop loop. it has more meaning of output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope. figure 21. voltage regulator equivalent circuit o i v o vid zout(s)=ll load vr figure 22. loop gain t1(s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer figure 23. loop gain t2(s) measurement set-up q2 q1 l o i c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer
isl62883, isl62883b 24 fn6891.4 june 21, 2011 jia wei, jwei@intersil.com, 919-405-3605 attention: 1. "analysis toolpak" add-in is required. to turn on, go to tools--add-ins, and check "analysis toolpak" 2. green cells require user input controller part number: phase number: 3 vin: 12 volts vo: 1.15 volts full load current: 51 amps estimated full-load efficiency: 87 % number of output bulk capacitors: 4 capacitance of each output bulk capacitor: 270 uf esr of each output bulk capacitor: 4.5 m r1 2.369 k r1 2.37 k esl of each output bulk capacitor: 0.6 nh r2 338.213 k r2 324 k number of output ceramic capacitors: 24 r3 0.530 k r3 0.536 k capacitance of each output ceramic capacitor: 10 uf c1 148.140 pf c1 150 pf esr of each output ceramic capacitor: 3 m c2 455.369 pf c2 390 pf esl of each output ceramic capacitor: 3 nh c3 40.069 pf c3 39 pf switching frequency: 300 khz inductance per phase: 0.36 uh cpu socket resistance: 0.9 m desired load-line slope: 1.9 m desired isum- pin current at full load: 40.9 ua t1 bandwidth: 212khz t2 bandwidth: 66khz (this sets the over-current protection level) t1 phase margin: 58.9 t2 phase margin: 89.3 inductor dcr 0.88 m place the 2nd compensator pole fp2 at: 2.2 rsum 3.65 k tune ki to get the desired loop gain bandwidth rntc 10 k tune the compensator gain factor ki: 1.3 rntcs 2.61 k (recommended ki range is 0.8~2) rp 11 k recommended value user selected value cn 0.406 uf cn 0.406 uf ri 606.036 ri 604 compensator parameters current sensing network parameters compensation & current sensing network design for intersil multiphase r^3 regulators for imvp-6.5 recommended value user-selected value operation parameters operation parameters use user-selected value (y/n)? performance and stability x fs (switching frequency) changing the settings in red requires deep understanding of control loop design loop gain, gain curve

! ! output impedance, gain curve "

# $ % & ' ( & n isl6288x

2 1 2 1 2 1 2 1 2 1 2 1 ) ( p p z z i v f s f s s f s f s i k s a loop gain, phase curve " ) )

* ( ! $ ! ! output impedance, phase curve ) )

* ( ! $ figure 24. screenshot of the compensator design spreadsheet
isl62883, isl62883b 25 fn6891.4 june 21, 2011 optional slew rate co mpensation circuit for 1-tick vid transition during a large vid transition, the dac steps through the vids at a controlled slew rate of 2.5s per tick (12.5mv), controlling output voltage v core slew rate at 5mv/s. figure 25 shows the waveforms of 1-tick vid transition. during 1-tick vid transition, the dac ou tput changes at approximately 15mv/s slew rate, but the dac cannot step through multiple vids to control the slew rate. instead, the control loop response speed determines v core slew rate. ideally, v core will follow the fb pin voltage slew rate. however, the controller senses the inductor current increase during th e up transition, as the i droop_vid waveform shows, and will droop the output voltage v core accordingly, making v core slew rate slow. similar behavior occurs during the down transition. to control v core slew rate during 1-tick vid transition, one can add the r vid -c vid branch, whose current i vid cancels i droop_vid . when v core increases, the time do main expression of the induced i droop change is expressed in equation 43 : where c out is the total output capacitance. in the mean time, the r vid -c vid branch current i vid time domain expression is shown in equation 44: it is desired to let i vid (t) cancel i droop_vid (t). so there are : and : the result is expressed in equation 47: and : for example: given ll = 1.9m , r droop =2.37k , c out = 1320f, dv core /dt = 5mv/us and dv fb /dt = 15mv/s, equation 47 gives r vid =2.37k and equation 48 gives c vid = 350pf. it?s recommended to select the calculated r vid value and start with the calculated c vid value and tweak it on the actual board to get the best performance. during normal transient response , the fb pin voltage is held constant, therefore is virtual ground in small signal sense. the r vid -c vid network is between the virtual ground and the real ground, and hence has no effe ct on transient response. voltage regulator thermal throttling figure 25. optional slew rate compensation circuit for1-tick vid transition x 1 e/a dac vid<0:6> rdroop idroop_vid vdac fb comp vcore vsssense vids rtn vss internal to ic rvid cvid vid<0:6> vfb vcore ivid idroop_vid ivid optional i droop t () c out ll r droop ------------------------ dv core dt ----------------- - 1e t ? c out ll ------------------------- ? ?? ?? ?? ?? = (eq. 43) i vid t () c vid dv fb dt ----------- - 1e t ? r vid c vid ------------------------------ ? ?? ?? ?? ?? = (eq. 44) c vid dv fb dt ----------- - c out ll r droop ------------------------ dv core dt ----------------- - = (eq. 45) r vid c vid c out ll = (eq. 46) r vid r droop = (eq. 47) c vid c out ll r droop ------------------------ dv core dt ----------------- - dv fb dt ----------- - ----------------- - = (eq. 48) ntc r ntc - + v ntc - + vr_tt# 1.24v 54ua internal to isl62882 figure 26. circuitry associated with the thermal throttling feature of the isl62882 r s 64ua 1.20v sw1 sw2
isl62883, isl62883b 26 fn6891.4 june 21, 2011 figure 26 shows the thermal thro ttling feature with hysteresis. an ntc network is connected between the ntc pin and gnd. at low temperature, sw1 is on and sw2 connects to the 1.20v side. the total current flowing out of the ntc pin is 60a. the voltage on ntc pin is higher than threshold voltage of 1.20v and the comparator output is low. vr_tt# is pulled up by the external resistor. when temperature increases, th e ntc thermistor resistance decreases so the ntc pin voltage drops. when the ntc pin voltage drops below 1.20v, the co mparator changes polarity and turns sw1 off and throws sw2 to 1.24v. this pulls vr_tt# low and sends the signal to start th ermal throttle. there is a 6a current reduction on ntc pin and 40mv voltage increase on threshold voltage of the comparator in this state. the vr_tt# signal will be used to change the cpu operation and decrease the power consumption. when th e temperature drops down, the ntc thermistor voltage will go up. if ntc voltage increases to above 1.24v, the comparator w ill flip back. the external resistance difference in these two conditions is expressed in equation 49: one needs to properly select the ntc thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. a regular resist or may need to be in series with the ntc thermistor to meet the threshold voltage values. for example, given panasonic ntc thermistor with b = 4700, the resistance will drop to 0.03322 of its nominal at +105c, and drop to 0.03956 of its nominal at +100c. if the required temperature hysteresis is +105c to +100c, the required resistance of ntc will be: therefore a larger value thermistor, such as 470k ntc should be used. at +105c, 470k ntc resistance becomes (0.03322 470k ) = 15.6k . with 60a on the ntc pin, the voltage is only (15.6k ? 60a) = 0.937v. this value is much lower than the threshold voltage of 1.20v. therefore, a regular resistor needs to be in series with the ntc. the required resistance can be calculated by equation 51: 4.42k is a standard resistor value. therefore, the ntc branch should have a 470k ntc and 4.42k resistor in series. the part number for the ntc thermistor is ertj0ev474j. it is a 0402 package. the ntc thermistor will be placed in the hot spot of the board. current balancing refer to figures 1 and 2. th e isl62883 achieves current balancing through matching the isen pin voltages. r s and c s form filters to remove the swit ching ripple of the phase node voltages. it is recommended to use rather long r s c s time constant such that the isen voltages have minimal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k and c s = 0.22f. layout guidelines table 5 shows the layout consider ations. the designators refer to the reference design shown in figure 27. 1.24v 54 a --------------- 1.20v 60 a --------------- ? 2.96k = (eq. 49) (eq. 50) 2.96k 0.03956 0.03322 ? () ------------------------------------------------------- 467k = (eq. 51) 1.20v 60 a --------------- 15.6k ? 4.4k = table 5. layout consideration pin name layout consideration ep gnd create analog ground plane underneath the controller and the analog signal processing components. don?t let the power ground plane overlap with the analog ground plane. avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane. 1 pgood no special consideration 2 psi# no special consideration 3 rbias place the rbias resistor (r16) in general proximity of the controller. low impedance connection to the analog ground plane. 4 vr_tt# no special consideration 5 ntc the ntc thermistor (r9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. usually it?s placed close to phase-1 high-side mosfet. 6 vw place the capacitor (c4) across vw and comp in close proximity of the controller 7 comp place the compensator components (c3, c6 r7, r11, r10 and c11) in general proximity of the controller. 8fb 9 isen3/fb2 a capacitor (c7) decouples it to vsum-. place it in general proximity of the controller. an optional capacitor is placed between this pin and comp. (it?s only used when the controller is configured 2-phase). place it in general proximity of the controller. 10 isen2 a capacitor (c9) decouples it to vsum-. place it in general proximity of the controller. 11 isen1 a capacitor (c10) decouples it to vsum-. place it in general proximity of the controller. 12 vsen place the vsen/rtn filter (c12, c13) in close proximity of the controller for good decoupling. 13 rtn
isl62883, isl62883b 27 fn6891.4 june 21, 2011 14 isum- place the current sensing circuit in general proximity of the controller. place c82 very close to the controller. place ntc thermistors r42 next to phase-1 inductor (l1) so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsum+ and vsum- signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. route r63 and r71 to the phase-1 side pad of inductor l1. route r88 to the output side pad of inductor l1. route r65 and r72 to the phase-2 side pad of inductor l2. route r90 to the output side pad of inductor l2. route r67 and r73 to the phase-3 side pad of inductor l3. route r92 to the output side pad of inductor l3. if possible. route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. the following drawings show the two preferred ways of routing current sensing traces. 15 isum+ 16 vdd a capacitor (c16) decouples it to gnd. place it in close proximity of the controller. 17 vin a capacitor (c17) decouples it to gnd. place it in close proximity of the controller. 18 imon place the filter capacitor (c21) close to the cpu. 19 boot1 use decent wide trace (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. 20 ugate1 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing phase1 trace to the phase-1 high-side mosfet (q2 and q8) source pins instead of general phase-1 node copper. 21 phase1 22 vssp1 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing vssp1 to the phase-1 low- side mosfet (q3 and q9) source pins instead of general power ground plane for better performance. 23 lgate1 24 pwm3 no special consideration. table 5. layout consideration (continued) pin name layout consideration inductor current-sensing traces vias inductor current-sensing traces 25 vccp a capacitor (c22) decouples it to gnd. place it in close proximity of the controller. 26 lgate2 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing vssp2 to the phase-2 low- side mosfet (q5 and q1) source pins instead of general power ground plane for better performance. 27 vssp2 28 phase2 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing phase2 trace to the phase-2 high-side mosfet (q4 an d q10) source pins instead of general phase-2 node copper. 29 ugate2 30 boot2 use decent wide trace (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. 31~37 vid0~6 no special consideration. 38 vr_on no special consideration. 39 dprslpvr no special consideration. 40 clk_en# no special consideration. other phase node minimize phase node copper area. don?t let the phase node copper overlap with/getting close to other sensitive traces. cut the power ground plane to avoid overlapping with phase node copper. other minimize the loop consisting of input capacitor, high-side mosfets and lo w-side mosfets (e.g.: c27, c33, q2, q8, q3 and q9). table 5. layout consideration (continued) pin name layout consideration
isl62883, isl62883b 28 fn6891.4 june 21, 2011 ------- ---- ---- 2.37k 560pf july 2009 jia wei 3-phase, dcr sensing isl62883 reference design optional optional ---- ---- ----- 1000pf 0.22uf 330pf 0.039uf 82.5 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 3.65k -----> 0.22uf 0.22uf dnp dnp irf7821 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf dnp irf7821 11k 1 1 10k ntc with the phase1 trace going to 2.61k same rule applies to other phases 3.65k 3.65k place near l1 irf7821 0.22uf 536 0.36uh 0.36uh 0.36uh irf7832 irf7832 irf7832 irf7832 irf7832 irf7832 820pf 270uf 270uf 270uf 270uf 1 the source of q2 and q8 route ugate1 trace in parallel layout note: 2.37k 390pf 0.47uf 7.87k 100 0.1uf ---- 604 ------------- ntc tbd 0.01uf ---- ------------- tbd 150pf route lgate1 trace in parallel with the vssp1 trace going to the source of q3 and q9 ----- 1of1 ------------- ---- ---- optional 324k 39pf 8.66k optional ------- dnp ------------- r4 c83 isen3 isen1 c7 vsssense 36 c6 c3 c4 psi# clk_en# dprslpvr 1000pf pgood r16 147k r9 10 isl62883hrz c18 10 c81 r109 14 0.22uf c16 19 r50 1uf isl6208 r40 41 r19 1.91k 1.91k vid3 vid4 u6 16 +5v 38 c74 c73 c72 c71 c68 c67 c66 c65 c64 c63 c61 c60 c59 c56 c55 c54 c50 c49 c48 c47 c43 c42 c41 c40 c11 40 33 23 22 r72 25 10uf 6 r12 r8 c15 r38 r41 vsum+ isen1 c9 0 0.22uf vsum+ vcore c10 vcore 0.22uf q5 isen2 c20 q7 c27 c39 0 r20 r18 27 32 26 c26 0 c32 c30 10uf 10uf c35 q13 l3 q9 l1 10uf c33 q2 r57 c31 q4 c28 10uf 10uf c34 q10 l2 c52 c57 c44 +5v c25 c21 vid5 vid6 vr_on r42 0 vid2 vid1 vid0 499 7 r17 c17 8 34 31 3 24 20 15 13 18 c82 vin r56 r90 vsum- 10k r65 r63 39 21 1uf vsum- r67 r73 10k r92 0.22uf 35 +5v 17 2 1 4 5 isen2 9 c22 c29 q6 q12 q8 r88 vsum- isen3 vsum+ u3 0 29 30 28 1 vin q11 10k vsum- r58 imon vsum+ 56uf 56uf c24 1uf r6 37 r10 r11 r26 r30 12 11 c13 c12 vccsense 10 vsssense r7 +1.1v +3.3v vr_tt# r110 r37 r23 q3 r71 ep clk_en# pgood psi# rbias vr_tt# ntc comp vw fb isen3 vid3 vid4 vid5 vid6 vr_on dprslpvr ugate2 boot2 phase2 vssp2 lgate2 vccp pwm3 lgate1 ugate1 boot1 imon vdd vin isum+ isum- rtn vsen isen1 phase1 vssp1 vid0 vid1 vid2 isen2 phase gnd lgate ugate vcc pwm fccm boot out out in out in in in out out in out in in in out in in in in out in in out out in in out in in in in in out in in out in out in in page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 figure 27. 3-phase reference design
isl62883, isl62883b 29 fn6891.4 june 21, 2011 reference design bill of materials qty reference value description manufacturer part number package 1 c11 390pf multilayer cap, 16v, 10% generic h1045-00391-16v10 sm0603 1 c12 330pf multilayer cap, 16v, 10% generic h1045-00331-16v10 sm0603 1 c13 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 1 c15 0.01f multilayer cap, 16v, 10% generic h1045-00103-16v10 sm0603 3 c16, c22, c26 1f multilayer cap, 16v, 20% generic h1045-00105-16v20 sm0603 1 c18 0.47f multilayer cap, 16v, 10% generic h1045-00474-16v10 sm0603 1 c20 0.1f multilayer cap, 16v, 10% generic h1045-00104-16v10 sm0603 8 c21, c7, c9, c10, c17, c30, c31, c32 0.22f multilayer cap, 16v, 10% generic h1045-00224-16v10 sm0603 2 c24, c25 56f radial sp series cap, 25v, 20% sanyo 25sp56m case-cc 6 c27, c28, c29, c33, c34, c35 10f multilayer cap, 25v, 20% generic h1065-00106-25v20 sm1206 1 c3 150pf multilayer cap, 16v, 10% generic h1045-00151-16v10 sm0603 4 c39, c44, c52, c57 270f spcap, 2v, 4.5mohm polymer cap, 2.5v, 4.5m panasonic kemet eefsx0d471e4 t520v477m2r5a(1)e4r5 1 c4 1000pf multilayer cap, 16v, 10% generic h1045-00102-16v10 sm0603 24 c40-c43, c47-c50, c53-c56, c59-c69, c78 10f multilayer cap, 6.3v, 20% murata panasonic tdk grm21br61c106ke15l ecj2fb0j106k c2012x5r0j106k sm0805 1 c6 39pf multilayer cap, 16v, 10% generic h1045-00390-16v10 sm0603 1 c81 820pf multilayer cap, 16v, 10% generic h1045-00821-16v10 sm0603 1 c82 0.039f multilayer cap, 16v, 10% generic h1045-00393-16v10 sm0603 1 c83 560pf multilayer cap, 16v, 10% generic h1045-00561-16v10 sm0603 3 l1, l2, l3 0.36h inductor, inductance 20%, dcr 5% nec-tokin panasonic mpch1040lr36 etqp4lr36afc 10mmx10mm 3 q2, q4, q6 n-channel power mosfet ir irf7821 pwrpakso8 6 q3, q5, q7, q9, q11, q13 n-channel power mosfet ir irf7832 pwrpakso8 3 q8, q10, q12 dnp 1 r10 536 thick film chip resistor , 1% generic h2511-05360-1/16w1 sm0603 1 r109 100 thick film chip resist or, 1% generic h2511-01000-1/16w1 sm0603 1 r11 2.37k thick film chip resist or, 1% generic h2511-02371-1/16w1 sm0603 1 r110 2.37k thick film chip resist or, 1% generic h2511-02371-1/16w1 sm0603 1 r12 499 thick film chip resistor , 1% generic h2511-04990-1/16w1 sm0603 1 r16 147k thick film chip resistor , 1% generic h2511-01473-1/16w1 sm0603 2 r17, r18 10 thick film chip resist or, 1% generic h2511-00100-1/16w1 sm0603 4 r19, r71, r72, r73 10k thick film chip resistor, 1% generic h2511-01002-1/16w1 sm0603 1 r23 1.91k thick film chip resist or, 1% generic h2511-01911-1/16w1 sm0603 1 r26 82.5 thick film chip resistor , 1% generic h2511-082r5-1/16w1 sm0603 5 r20, r40, r56, r57, r58 0 thick film chip resistor, 1% generic h2511-00r00-1/16w1 sm0603 1 r30 604 thick film chip resistor , 1% generic h2511-06040-1/16w1 sm0603
isl62883, isl62883b 30 fn6891.4 june 21, 2011 4 r37, r88, r90, r92 1 thick film chip resistor, 1% generic h2511-01r00-1/16w1 sm0603 1 r38 11k thick film chip resistor , 1% generic h2511-01102-1/16w1 sm0603 1r4 dnp 1 r41 2.61k thick film chip resistor, 1% generic h2511-02611-1/16w1 sm0603 1 r42 10k ntc thermistor, 10k ntc panasonic ert-j1vr103j sm0603 1 r50 7.87k thick film chip resist or, 1% generic h2511-07871-1/16w1 sm0603 1 r6 8.66k thick film chip resist or, 1% generic h2511-08662-1/16w1 sm0603 3 r63, r65, r67 3.65k thick film chip re sistor, 1% generic h2511-03651-1/16w1 sm0805 2 r8, r9 dnp 1 r7 324k thick film chip resist or, 1% generic h2511-03243-1/16w1 sm0603 1 u3 synchronous rectified mosfet driver intersil isl6208cbz soic8_150_50 1 u6 imvp-6.5 pwm controller intersil isl62883hrtz qfn-40 reference design bill of materials (continued) qty reference value description manufacturer part number package
isl62883, isl62883b 31 fn6891.4 june 21, 2011 typical performance figure 28. 3-phase ccm ef ficiency, vid = 1.075v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 29. 3-phase ccm load line, vid = 1.075v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 30. 2-phase ccm efficiency, vid = 0.875v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 31. 2-phase ccm load line, vid = 0.875v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 32. 1-phase dem efficiency, vid = 0.875v, v in1 =8v, v in2 = 12.6v and v in3 = 19v figure 33. 1-phase dem load line, vid = 0.875v, v in1 =8v, v in2 = 12.6v and v in3 = 19v 70 72 74 76 78 80 82 84 86 88 90 92 0 5 10 15 20 25 30 35 40 45 50 55 60 65 i out (a) efficiency(%) v in = 8v v in = 12v v in = 19v 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 i out (a) v out (v) 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i out (a) efficiency (%) v in = 8v v in = 19v v in = 12v 0.825 0.835 0.845 0.855 0.865 0.875 0.885 0 101112131415 i out (a) v out (v) 123456789 60 65 70 75 80 85 90 95 0.1 1 10 100 i out (a) efficiency (%) v in = 8v v in = 19v v in = 12v 0.825 0.835 0.845 0.855 0.865 0.875 0.885 0 101112131415 i out (a) v out (v) 123456789
isl62883, isl62883b 32 fn6891.4 june 21, 2011 figure 34. soft-start, v in = 19v, i o = 0a, vid = 0.95v, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 35. shut down, v in = 19v, i o = 1a, vid = 0.95v, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 36. clk_en# delay, v in = 19v, i o =2a, vid=1.5v, ch1: phase1, ch2: v o , ch3: imon, ch4: clk_en# figure 37. pre-charged start up, v in = 19v, vid = 0.95v, ch1: phase1, ch2: v o , ch3: imon, ch4: vr_on figure 38. steady state, v in = 19v, i o = 51a, vid = 0.95v, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 39. imon, vid = 1.075v typical performance (continued) 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 40 45 50 i out (a) imon-vss sense (mv) v in = 8v v in = 19v spec v in = 12v
isl62883, isl62883b 33 fn6891.4 june 21, 2011 figure 40. load transient response with overshoot reduction function disabled, v in =12v, sv clarksfield cpu test condition: vid = 0.95v, i o = 12a/51a, di/dt = ?fastest?, ll = 1.9m figure 41. load transient response with overshoot reduction function disabled, v in =12v, sv clarksfield cpu test condition: vid = 0.95v, i o = 12a/51a, di/dt = ?fastest?, ll = 1.9m figure 42. load transient response with overshoot reduction function disabled, v in =12v, sv clarksfield cpu test condition: vid = 0.95v, i o = 12a/51a, di/dt = ?fastest?, ll = 1.9m figure 43. load transient response with overshoot reduction function disabled, v in =12v, sv clarksfield cpu test condition: vid = 0.95v, i o = 12a/51a, di/dt = ?fastest?, ll = 1.9m figure 44. 2-phase mode load insertion response with overshoot reduction function disabled, 3-phase configuration, psi# = 0, dprslpvr = 0, v in = 12v, vid = 0.875v, i o =4a/17a, di/d = ?fastest figure 45. 2-phase mode load insertion response with overshoot reduction function disabled, 3-phase configuration, psi# = 0, dprslpvr=0, v in = 12v, vid = 0.875v, i o = 4a/17a, di/dt = ?fastest? typical performance (continued)
isl62883, isl62883b 34 fn6891.4 june 21, 2011 figure 46. phase adding/dropping (psi# toggle), i o = 15a, vid = 1.075v, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 47. deeper sleep mode entry/exit, i o = 1.5a, hfm vid = 1.075v, lfm vid = 0.875v, deeper sleep vid = 0.875v, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 48. vid on the fly, 1.075v/0.875v, 3-phase configuration, psi#=1, dprslpvr=0, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 49. vid on the fly, 1.075v/0.875v, 3-phase configuration, psi#=0, dprslpvr=0, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 50. vid on the fly, 1.075v/0.875v, 3-phase configuration, psi# = 0, dprslpvr = 1, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 figure 51. vid on the fly, 1.075v/0.875v, 3-phase configuration, psi# = 1, dprslpvr = 1, ch1: phase1, ch2: v o , ch3: phase2, ch4: phase3 typical performance (continued)
isl62883, isl62883b 35 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6891.4 june 21, 2011 for additional products, see www.intersil.com/product_tree figure 52. load transient response with overshoot reduction function enabled, v in =12v, sv clarksfield cpu test condition: vid = 0.95v, i o = 12a/51a, di/dt = ?fastest?, ll = 1.9m , ch1: lgate1, ch2: v o , ch3: lgate2, ch4: isl6208 lgate figure 53. reference design loop gain t2(s) measurement result figure 54. imon, vid = 1.075v figure 55. reference design fdim result typical performance (continued) gain phase margin 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 40 45 50 i out (a) imon-vss sense (mv) v in = 8v v in = 19v spec v in = 12v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 frequency (hz) 1k 10k 100k 1m z(f) (m ? ) psi# = 0, dprslpvr = 0, 2-phase ccm psi# = 1, dprslpvr = 0, 3-phase ccm
isl62883, isl62883b 36 fn6891.4 june 21, 2011 package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4
isl62883, isl62883b 37 fn6891.4 june 21, 2011 package outline drawing l48.6x6 48 lead thin quad flat no-lead plastic package rev 1, 4/07 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 a b pin 1 index area (4x) 0.15 6 6.00 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 0.80 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ ) ( 4. 40 ) ( 48x 0 . 20 ) ( 48x 0 . 65 ) ( 44 x 0 . 40 ) 0.05 m c

▲Up To Search▲

Price & Availability of ISL62883IRTZ

	To Download ISL62883IRTZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .